1. Technical Field
The present invention relates to an oversampling system, a decoding LSI chip, and an oversampling method for decoding and then oversampling digital audio compressed in units of frames. More specifically, the present invention relates to an oversampling system, a decoding LSI chip, and an oversampling method capable of decreasing the memory capacity of an output buffer used to oversample decoded data.
2. Related Art
Recently, the digital audio technology often uses the MPEG2 AAC (Advanced Audio Coding) 5.1 channel as MPEG audio. Reproduction of its contents needs to decode MPEG audio data. Decoding the MPEG audio data generates PCM audio data. In many cases, after oversampling the PCM audio data, DA conversion of the oversampled data is performed.
FIG. 6 shows a conventional example of oversampling after decoding performed on a dedicated LSI chip. The following describes an example of decoding to perform MPEG2 AAC 5.1 channel decoding and then double oversampling.
In FIG. 6, a dedicated LSI chip 100 is composed of a DSP and has an AAC decoding function and an oversampling function. An AAC decoder 101 receives an input stream signal (AAC bit stream signal) and performs decoding a frame by frame basis. An oversampling section 102 oversamples a decoding result and stores it in an output buffer 110.
The AAC decoder 101 performs frame-based decoding and temporarily writes data of 1,024 words (samples) per channel to the output buffer 110. The oversampling section 102 double oversamples the decoded data (PCM audio data) of 1,024 samples per channel that is decoded by the AAC decoder 101, and is temporarily written to the output buffer 110. The oversampling section 102 writes the data as PCM audio data of 2,048 words per frame to the output buffer 110.
The output buffer 110 is provided with an output buffer area A and an output buffer area B. Accordingly, the output buffer 110 contains:
“a number of decoded output samples×2 (areas A and B)×2 (double oversampling)” per channel. In the case of 5.1 channels, the output buffer 110 has the memory capacity of:
“6 (channels)×1,024 (the number of samples)×2 (areas A and B)×2 (double oversampling)=24,576 words”.
FIG. 7 illustrates operations of the output buffer 110 in FIG. 6 according to a conventional example.
At the beginning of processing a current frame N as shown in FIG. 7(a), the output buffer area A of the output buffer 110 records a result of oversampling of a preceding frame N−1 (2,048 words/channel) for 5.1 channels such as L, R, LS, RS, C, and LEF. Frame N is subject to a process of writing the oversampling result to the output buffer area B (2,048 words/channel) and outputting data from the output buffer area A to the outside (DAC and the like) of the dedicated LSI chip.
In FIG. 7(b), the output buffer area A for each channel contains data which is stored in the earlier output buffer area B. The output buffer area B (earlier output buffer area A) is empty and will contain an oversampling result for the next frame N+1. This example uses the cyclic buffer configuration that shifts a point (address) to start outputting each channel data to the higher order for 2,048 words.
The above-mentioned procedure is repeated to sequentially output data for frames N, N+1, N+2, and so on to the outside.
FIGS. 7(c) and 7(d) show timings for decoding and oversampling. As shown in FIG. 7(c), while data is output from the preceding frame N−1, the next frame N is decoded, and then the decoded data of the frame N is oversampled successively. An oversampling result (oversampled data) is written to the output buffer area B.
There has been described the conventional AAC decoding and oversampling processes using the dedicated LSI chip. According to the conventional example, however, each channel requires the buffer memory capacity four times as much as the number of data samples.
A conventional-art document (e.g., see patent document 1) related to the present invention discloses the following configuration. That is, a DSP processing result is written to a double-buffered output buffer that cyclically changes write and read modes. The DSP processing result is read at a specified sampling cycle and is output to the outside.
[Patent document 1]
Japanese Patent Application Laid-Open Publication No. 2004-12967